FIG. 1 shows a typical switching regulator 100, emphasizing the output section, while FIG. 2 shows pertinent switching waveforms for regulator 100. The control section of the regulator, not shown in detail, typically comprises an error amplifier with feedback components, a modulator circuit, and level shifters, collectively 110, to translate the resulting desired pulse widths into signal levels suitable for the Drivers 1 and 2. A reference voltage is typically applied to the non-inverting input of error amplifier contained in control section 110. The output of the error amplifier drives a pulse width modulator, PWM. The PWM outputs driver control signals shown as PWM1 and PWM2 which drive Driver 1 and Driver 2, respectively.
Drivers 1 and 2 take PWM1 and PWM2 and drive relatively high currents into the gates of NMOS output devices M1 and M2. These signals are shown in FIG. 1 as UGATE and LGATE. The drivers normally also incorporate a non-overlap circuit (not shown), that prevents M1 and M2 from both conducting at the same time.
The desired output is at the node shown as PHASE, which is at the source of M1 and the drain of M2. During operation of regulator 100 PHASE switches between levels approaching VIN (when M1 on) and ground (when M2 on). PHASE then passes through a low pass filter comprising LF in series with CF, to become VOUT across load RL. Optional voltage and current feedback is shown, for instance, to maintain a specified relationship between output voltage and output current.
For reasons of economy, M1 and M2 are typically both double-diffused NMOS (DMOS). The driver for M2, the source of M2 being at ground, is typically powered from a supply (shown as LGATE Supply), which is also returned to ground.
It is desirable that M1, whose source is at node PHASE, has a driver and driver supply that is related to PHASE. Specifically, the power supply should move up and down with PHASE, keeping a relatively constant voltage with respect to PHASE. That supply, shown as BOOT supply, typically includes a diode such as D1 and capacitor such as the BOOT Cap shown. The voltage at node BOOT with respect to PHASE is approximately that provided by the BOOT supply.
The voltage at BOOT could be made related to ground rather than PHASE, if D1 was replaced with a direct connection and the BOOT cap was omitted. The BOOT supply voltage level would need to be higher than the VIN supply level (typically 5 V higher, or more) so that M1 can be strongly turned on, and when on, be in a low RDSon condition. This mode of operation is less desirable than a floating BOOT supply, as it requires higher voltage components and generates more wasted power. Further discussion will assume that a floating BOOT supply is used.
Very often the LGATE supply and the BOOT supply are the same supply. This might be due to a lack of pins available on an IC, for instance, when D1 is integrated within the IC.
There are conflicting requirements placed on the voltage selected for the BOOT and/or the LGATE supplies. The RDSon of a DMOS such as M1 or M2 contributes significantly to the power loss, or lack of power efficiency, of regulator 100. The average load current, Iload, flowing through inductor LF also flows through M1 or M2. The power loss in M1 or M2 is directly proportional to its RDSon multiplied by the square of Iload. As the RDSon of a DMOS can be improved (made lower) over a fairly wide range by increasing the Gate drive level, it is beneficial to use as high a value of BOOT or LGATE supply as the driver circuit can handle based on the voltage drop (RDSon component) considerations across M1 or M2.
A second major component of loss of efficiency for regulator 100 is the charge that must be inserted and removed from the DMOS' (M1 and M2) gate capacitance, once every switching cycle. Increasing the gate drive voltage increases the magnitude of the charge that must be inserted and removed each cycle, which increases the average current during switching. This increased average current gets dropped through the driver from an increased supply voltage. The gate capacitance induced power loss is therefore proportional to the square of the drive voltage, making it beneficial to use as low a driver voltage as possible.
FIG. 3 shows an exemplary plot of efficiency versus load current for higher and lower gate driver voltage supply levels for the regulator shown in FIG. 1. For purposes of simplicity, it is assumed that the BOOT and LGATE supplies are the same supply. The RDSon component of power loss through M1 and M2 is seen to tend to dominate at relatively high load currents, and the gate charge component of power loss tends to dominate at low load current levels. Accordingly, efficiency cannot be optimized for both high and low current operation. Instead, a relatively high fixed gate driver supply voltage is generally selected for regulator operation, thus wasting power when running at low load current levels. What is needed is a pulse width modulated converter design that provides different gate driver supply voltages for different load current levels that removes the tradeoff in efficiency between high load current and low load current operation.